1. Field of the Invention
The present invention relates to semiconductor devices having memory cells that require a periodic refresh operation. More particularly, the present invention relates to a high voltage generator and a high voltage supply method for use in such semiconductor devices, suitable for performing a refresh operation internally, while operating externally under the same timing conditions as static random access memory (SRAM).
2. Description of Related Art
In semiconductor random access memory (RAM) devices, data is stored at a specific location in a memory cell array designated by an individual address. The data is stored in basic RAM cells such as static RAM (SRAM) cells and dynamic RAM (DRAM) cells. The SRAM cell has a static latching structure (typically comprised of six transistors, or four transistors and two resistors) that can store data without a refresh operation as long as an external power supply is maintained. The DRAM cell is comprised of one storage element (typically a capacitor) and one access transistor. In the DRAM cell, high state data is stored in the capacitor, which gradually discharges over time. Therefore, high state data cannot be stored in a DRAM cell for long unless the DRAM cell is periodically refreshed.
The periodic refresh operation required for a DRAM cell to prevent charge leakage and consequential data loss requires a circuit to perform the refresh operation before such a loss of data occurs. An Early DRAM (especially, DRAM operating externally having the same timing conditions as SRAM) can perform a refresh function under the control of an external storage device controller. Currently, most DRAM memory devices possess internal refresh circuitry and can perform an internal refresh function.
A benefit DRAM is that a DRAM cell is smaller than a SRAM cell produced by a similar process, but much more data can be stored in the smaller DRAM cell than in the larger SRAM cell. Therefore, it is desirable to develop DRAM that can replace SRAM without impacting the operating conditions of peripheral circuits.
However, it is important to guarantee effective operation of a DC generator for reliable performance of a semiconductor device. Thus, many attempts at stable operation of a DC generator have been made. A method for controlling a booster circuit for providing a high voltage VPP higher than an external power supply voltage to internal circuits needing the high voltage VPP such as word line drivers in a memory device having DRAM memory cells is disclosed in U.S. Pat. No. 5,610,863, issued on Mar. 11, 1997, to Yamada. In FIG. 2 of the patent, a booster circuit generates a voltage VPP using an oscillator and a boosting capacitor to charge a bias capacitor via a transistor to a voltage that is higher than an input power supply voltage. A word line driver switches VPP to a particular word line in response to a selection signal provided during an xe2x80x9cactivexe2x80x9d period of memory operation. The particular word line selection provides a refresh charge to a memory cell. Since a typical boosting operation of the booster circuit is longer than the active period, it is possible to provide a voltage required for a read operation to the word line in a short cycle period, thereby improving the reliability of the memory device.
The patent, however, does not provide a solution for a voltage level drop problem that occurs during VPP charge supply in an initial active period. The voltage level drop problem that occurs during initial VPP charge consumption will be clarified in the following explanation.
Word line, or W/L, enable time for memory cell access of conventional DRAM is determined on the basis of a randomly applied external timing signal via a particular W/L path, and a W/L path is enabled through the shortest path from the external timing to minimize the access time. In this case, the enabling time for the VPP supply is determined on the basis of the W/L enabling time to minimize charge consumption due to leakage. Since the VPP generator generates charge by a boosting method using a pumping capacitor, a pre-charge time of a boosting node can be lengthy. Because the starting time of the charge supply for the boosting operation is based on the W/L enable time, under the condition that the stand-by VPP level is maintained in stand-by operation mode, the starting time to supply charge in the VPP generator is delayed compared with the initial starting time to consume the VPP charge. Therefore, in a 3.3 volt synchronous dynamic random access memory (SDRAM) case, there is a voltage drop of about 0.5xcx9c0.7 volt from a reference VPP at initial VPP charge consumption. This voltage drop results in a time delay in a circuit chain using the VPP, and, in the worst case, failure of memory cell operation. In FIG. 3, the VPP drop is shown graphically when the VPP generator is enabled (refer to VPP_EN) based on W/L enable time (refer to W/L). In FIG. 3, time points t1 and t2 indicate initial charge consumption time of the VPP charge, and initial VPP charge supply time, respectively. According to this operation timing, a voltage level drop indicated by G1 occurs, and can result in performance deterioration of a semiconductor device due to failure of memory cell operation.
Thus, there is a demonstrated need to prevent the above-described voltage drop during a DRAM refresh operation to ensure reliability of the memory device.
It is therefore a feature of an embodiment of the present invention to provide an improved semiconductor device adapted VPP generator and an operation method thereof.
It is another feature of an embodiment of the present invention to provide an operation control method to prevent a VPP level drop by effectively controlling the VPP generator.
It is another feature of an embodiment of the present invention to provide a semiconductor device that can reduce or minimize a voltage drop at VPP charge consumption, and a VPP supplying method therefore.
According to a preferred embodiment of the present invention, there is provided a semiconductor memory device, preferably for performing a static random access memory operation, including an internal power supply voltage generator selectively providing an internal voltage that is higher than an external power supply voltage, and including a word line driving circuit coupled to the internal voltage, wherein a starting point of time of a charge supply operation of the high voltage generator occurs prior to a starting point of time of charge consumption of the high voltage in the word line driving circuit.
According to another embodiment of the present invention, there is provided a semiconductor device which includes an internal power supply voltage generator for generating an internal power supply voltage coupled to an external power supply voltage, an internal circuit coupled to the internal power supply voltage, and a driving control signal generator for applying a driving control signal to the internal power supply voltage generator wherein a starting point of time for charge supply of the internal power supply voltage generator is earlier than a starting point of time of charge consumption of the internal power supply voltage in the internal circuit. The voltage level of the internal power supply voltage in the internal power supply voltage generator is preferably higher than that of the external power supply voltage. The VPP is preferably supplied to a stand-by VPP output node in response to a driving control signal activated in a memory cell access operation period. A DRAM cell may be coupled to the internal circuit, and the semiconductor memory device preferably performs a static random access memory operating interface.
According to another embodiment of the present invention, a semiconductor memory device performing a static random access memory interface provides a plurality of refresh type memory cells provided in intersections of a plurality of word lines and a plurality of bit lines, a high voltage generator for providing a high voltage to a stand-by high voltage output node in response to a driving control signal activated in a memory cell access operation period, wherein the high voltage is higher than a power source voltage, an internal circuit related to word line driving for selecting a word line among the plurality of word lines using the high voltage in response to command information and address information, and a driving control signal generator generating the driving control signal in response to the command information, wherein a starting point of time for driving the high voltage generator is earlier than a starting point of time of charge consumption at the stand by high voltage output node in the memory cell access operation period. The starting point of time of charge consumption preferably corresponds to the enabling point of time of the selected word line.
According to another embodiment of the present invention, a method for controlling a high voltage generator of a semiconductor memory device having a plurality of refresh type memory cells connected to intersections of a plurality of word lines and a plurality of bit lines, and performing a static random access memory operating interface is provided, wherein the method includes receiving external command information applied in a memory cell access operation period and providing a driving control signal to the high voltage generator based on the external command information, wherein a starting point of time of a charge supply operation of the high voltage generator occurs prior to a starting point of time of charge consumption at an output node of the high voltage generator. The command information preferably relates to read, write and refresh signals.
According to another embodiment of the present invention, a method for controlling a high voltage generator of a semiconductor memory device having a plurality of refresh type memory cells connected to intersections of a plurality of word lines and a plurality of bit lines, and performing a static random access memory operating interface, comprising generating a command output signal in response to an external command signal applied in a memory cell access operation period is provided, wherein the method includes supplying a high voltage to an internal circuit by enabling the high voltage generator during generation of the command output signal, and delaying the command output signal and providing the delayed command output signal to the internal circuit for selecting a word line among the plurality of word lines, wherein the selected word line is activated at a point of time that is delayed compared with a supply point of time of the high voltage. The command output signal may preferably be applied to an address selection decoder, the address selection decoder generating a first address decoding signal. The internal circuit may include a word line enable circuit, a word line driver controller, and a word line. The charge consumption operation preferably occurs in the internal circuit after the high voltage is supplied, and may occur before enabling of the selected word line.
According to the present invention, reliability of a memory cell access operation may be greatly improved and layout size may be reduced, due to minimization of the voltage drop that occurs at consumption of the VPP charge, which allows a reduction in the size of a pumping capacitor in the VPP generator.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.